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| GS8170DW36/72C-333/300/250/200 209-Bump BGA Commercial Temp Industrial Temp Features * Double Late Write mode, Pipelined Read mode * JEDEC-standard SigmaRAMTM pinout and package * 1.8 V +150/-100 mV core power supply * 1.5 V or 1.8 V CMOS Interface * ZQ controlled user-selectable output drive strength * Dual Cycle Deselect * Burst Read and Write option * Fully coherent read and write pipelines * Echo Clock outputs track data output drivers * Byte write operation (9-bit bytes) * 2 user-programmable chip enable inputs * IEEE 1149.1 JTAG-compliant Serial Boundary Scan * 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package * Pin-compatible with future 36Mb, 72Mb, and 144Mb devices 18Mb 1x1Dp CMOS I/O Double Late Write SigmaRAMTM Functional Description 200 MHz-333 MHz 1.8 V VDD 1.5 V or 1.8 V I/O SigmaRAM Family Overview GS8170DW36/72 SigmaRAMs are built in compliance with the SigmaRAM pinout standard for synchronous SRAMs. They are 18,874,368-bit (18Mb) SRAMs. This family of wide, very low voltage CMOS I/O SRAMs is designed to operate at the speeds needed to implement economical high performance networking systems. Bottom View 209-Bump, 14 mm x 22 mm BGA 1 mm Bump Pitch, 11 x 19 Bump Array Because SigmaRAMs are synchronous devices, address data inputs and read/write control inputs are captured on the rising edge of the input clock. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. RAMs support pipelined reads utilizing a rising-edgetriggered output register. They also utilize a Dual Cycle Deselect (DCD) output deselect protocol. RAMs are offered in a number of configurations including Late Write, Double Late Write, and Double Data Rate (DDR). The logical differences between the protocols employed by these RAMs mainly involve various approaches to write cueing and data transfer rates. The RAMTM family standard allows a user to implement the interface protocol best suited to the task at hand. RAMs are implemented with high performance CMOS technology and are packaged in a 209-bump BGA. Parameter Synopsis Key Fast Bin Specs Cycle Time Access Time Symbol tKHKH tKHQV - 333 3.0 ns 1.6 ns Rev: 2.04 5/2005 1/27 (c) 2002, GSI Technology, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8170DW36/72C-333/300/250/200 256K x 72 Common I/O--Top View (Package C) 1 A B C D E F G H J K L M N P R T U V W * 2002.06 * 2 DQg DQg DQg DQg DQc DQc DQc DQc DQc CQ2 DQh DQh DQh DQh DQh DQd DQd DQd DQd 3 A Bc Bh VSS VDDQ VSS VDDQ VSS VDDQ CK VDDQ VSS VDDQ VSS VDDQ VSS NC A TMS 4 E2 Bg Bd NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDI 5 A NC NC (144M) NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC NC (72M) A A 6 ADV W E1 MCL VDD ZQ EP2 EP3 MCH MCL MCH MCL MCH MCL VDD MCL A A1 A0 7 A A NC NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC NC (36M) A A 8 E3 Bb Be NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDO 9 A Bf Ba VSS VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ VSS NC A TCK 10 DQb DQb DQb DQb DQf DQf DQf DQf DQf CQ1 DQa DQa DQa DQa DQa DQe DQe DQe DQe 11 DQb DQb DQb DQb DQb DQf DQf DQf DQf CQ1 DQa DQa DQa DQa DQe DQe DQe DQe DQe DQg DQg DQg DQg DQg DQc DQc DQc DQc CQ2 DQh DQh DQh DQh DQd DQd DQd DQd DQd 11 x 19 Bump BGA--14 x 22 mm2 Body--1 mm Bump Pitch Note: Users of CMOS I/O SigmaRAMs may wish to connect "NC, VREF" and the "NC, CK" pins to VREF (i.e., VDDQ/2) to allow alternate use of future HSTL I/O SigmaRAMs. Rev: 2.04 5/2005 2/27 (c) 2002, GSI Technology, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8170DW36/72C-333/300/250/200 512K x 36 Common I/O--Top View (Package C) 1 A B C D E F G H J K L M N P R T U V W * 2002.06 * 2 NC NC NC NC DQc DQc DQc DQc DQc CQ2 NC NC NC NC NC DQd DQd DQd DQd 3 A Bc NC VSS VDDQ VSS VDDQ VSS VDDQ CK VDDQ VSS VDDQ VSS VDDQ VSS NC A TMS 4 E2 NC Bd NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDI 5 A A NC (144M) NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC NC (72M) A A 6 ADV W E1 MCL VDD ZQ EP2 EP3 MCH MCL MCH MCL MCH MCL VDD MCL A A1 A0 7 A A NC NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC NC (36M) A A 8 E3 Bb NC NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDO 9 A NC Ba VSS VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ VSS NC A TCK 10 DQb DQb DQb DQb NC NC NC NC NC CQ1 DQa DQa DQa DQa DQa NC NC NC NC 11 DQb DQb DQb DQb DQb NC NC NC NC CQ1 DQa DQa DQa DQa NC NC NC NC NC NC NC NC NC NC DQc DQc DQc DQc CQ2 NC NC NC NC DQd DQd DQd DQd DQd 11 x 19 Bump BGA--14 x 22 mm2 Body--1 mm Bump Pitch Note: Users of CMOS I/O SigmaRAMs may wish to connect "NC, VREF" and the "NC, CK" pins to VREF (i.e., VDDQ/2) to allow alternate use of future HSTL I/O SigmaRAMs. Rev: 2.04 5/2005 3/27 (c) 2002, GSI Technology, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8170DW36/72C-333/300/250/200 Pin Description Table Symbol A ADV Bx W E1 E2 & E3 EP2 & EP3 CK CQ, CQ DQ MCH MCL Description Address Advance Byte Write Enable Write Enable Chip Enable Chip Enable Chip Enable Program Pin Clock Echo Clock Data I/O Must Connect High Must Connect Low Type Input Input Input Input Input Input Mode Input Input Output Input/Output Input Input Comments -- Active High Active Low Active Low Active Low Programmable Active High or Low To be tied directly to VDD, VDDQ or VSS Active High Three State - Deselect via E2 or E3 False Three State Active High To be tied directly to VDD or VDDQ Active Low To be tied directly to VSS Low = Low Impedance [High Drive] High = High Impedance [Low Drive] To be tied directly to VDDQ or VSS Active High -- -- -- Not connected to die or any other pin 1.8 V Nominal 1.5 or 1.8 V Nominal -- ZQ TCK TDI TDO TMS NC VDD VDDQ VSS Output Impedance Control Test Clock Test Data In Test Data Out Test Mode Select No Connect Core Power Supply Output Driver Power Supply Ground Mode Input Input Input Output Input -- Input Input Input Operation Control All address, data and control inputs (with the exception of EP2, EP3, ZQ, and the mode pins, L6, M6, and J6) are synchronized to rising clock edges. Data in is captured on both rising and falling edges of CK. Read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable inputs will deactivate the device. It should be noted that ONLY deactivation of the RAM via E2 and/or E3 deactivates the Echo Clocks, CQ1-CQ2. Rev: 2.04 5/2005 4/27 (c) 2002, GSI Technology, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8170DW36/72C-333/300/250/200 Read Operations Pipelined Read Read operation is initiated when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2, and E3) are active, the write enable input signal (W) is deasserted high, and ADV is asserted low. The address presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins Single Data Rate (SDR) Pipelined Read. Read A CK Address ADV E1 W DQ CQ Q(A) Q(B) Q(C) Q(D) A B C D E Deselect Read B Read C Read D Write Operations Write operation occurs when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2, and E3) are active, the write enable input signal (W) is asserted low, and ADV is asserted low. Rev: 2.04 5/2005 5/27 (c) 2002, GSI Technology, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8170DW36/72C-333/300/250/200 Double Late Write Double Late Write means that Data In is required on the third rising edge of clock. Double Late Write is used to implement Pipeline mode NBT SRAMs. SigmaRAM Double Late Write with Pipelined Read Read CK Write Read Write Read Address A B C D E F ADV /E1 /W DQ QA DB QC DD CQ Key Hi-Z Access Byte Write Control The Byte Write Enable inputs (Bx) determine which bytes will be written. Any combination of Byte Write Enable control pins, including all or none, may be activated. A Write Cycle with no Byte Write inputs active is a write abort cycle. Example of x36 Byte Write Truth Table Function Read Write Byte A Write Byte B Write Byte C Write Byte D Write all Bytes Write Abort W H L L L L L L Ba X L H H H L H Bb X H L H H L H Bc X H H L H L H Bd X H H H L L H Rev: 2.04 5/2005 6/27 (c) 2002, GSI Technology, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8170DW36/72C-333/300/250/200 Two Byte Write Control Example with Double Late Write SigmaRAM Write CK Write Write Non-Write Write Address A B C D E F ADV /E1 ADV /BA /BB DA DQA0-DQA8 DA DQB0-DQB8 DC DB DE CQ Rev: 2.04 5/2005 7/27 (c) 2002, GSI Technology, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8170DW36/72C-333/300/250/200 Special Functions Burst Cycles Although SRAMs can sustain 100% bus bandwidth by eliminating the bus turnaround cycle in Double Late Write mode, burst read or burst write cycles may also be performed. SRAMs provide an on-chip burst address generator that can be utilized, if desired, to simplify burst read or write implementations. The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode. SigmaRAM Pipelined Burst Reads with Counter Wraparound Read A CK Address ADV E1 W DQA0-DQA8 CQ Q(A) Q(A+1) Q(A+2) Q(A+3) Q(A) A Cont A+1 Cont A+2 Cont A+3 Cont A Deselect SigmaRAM Double Late Write SRAM Burst Writes with Counter Wrap-around Write CK Continue Continue Continue Continue Address Internal Address ADV A2 XX XX XX XX XX A2 A3 A0 A1 A2 Counter Wraps /E1 /W DQ D2 D3 D0 D1 D2 CQ Rev: 2.04 5/2005 8/27 (c) 2002, GSI Technology, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8170DW36/72C-333/300/250/200 Burst Order The burst address counter wraps around to its initial state after four internal addresses (the loaded address and three more) have been accessed. SigmaRAMs always count in linear burst order. Linear Burst Order A[1:0] 1st address 2nd address 3rd address 4th address 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 Note: The burst counter wraps to initial state on the 5th rising edge of clock. Echo Clock RAMs feature Echo Clocks, CQ1, CQ2, CQ1, and CQ2 that track the performance of the output drivers. The Echo Clocks are delayed copies of the main RAM clock, CK. Echo Clocks are designed to track changes in output driver delays due to variance in die temperature and supply voltage. The Echo Clocks are designed to fire with the rest of the data output drivers. SigmaRAMs provide both in-phase, or true, Echo Clock outputs (CQ1 and CQ2) and inverted Echo Clock outputs (CQ1 and CQ2). It should be noted that deselection of the RAM via E2 and E3 also deselects the Echo Clock output drivers. The deselection of Echo Clock drivers is always pipelined to the same degree as output data. Deselection of the RAM via E1 does not deactivate the Echo Clocks. Programmable Enables RAMs feature two user-programmable chip enable inputs, E2 and E3. The sense of the inputs, whether they function as active low or active high inputs, is determined by the state of the programming inputs, EP2 and EP3. For example, if EP2 is held at VDD, E2 functions as an active high enable. If EP2 is held to VSS, E2 functions as an active low chip enable input. Programmability of E2 and E3 allows four banks of depth expansion to be accomplished with no additional logic. By programming the enable inputs of four SRAMs in binary sequence (00, 01, 10, 11) and driving the enable inputs with two address inputs, four SRAMs can be made to look like one larger RAM to the system. Rev: 2.04 5/2005 9/27 (c) 2002, GSI Technology, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8170DW36/72C-333/300/250/200 Example Four Bank Depth Expansion Schematic--1x1Dp A0-An E1 CK W DQ0-DQn A0-An - 2 An - 1 An Bank 0 A E3 E2 E1 CK W CQ CQ EP3 0 0 DQ EP2 A0-An - 2 An - 1 An Bank 1 A E3 E2 E1 CK W CQ EP3 1 0 DQ EP2 A0-An - 2 An - 1 An Bank 2 A E3 E2 E1 CK W EP3 DQ EP2 CQ 0 1 A0-An - 2 An - 1 An Bank 3 A E3 E2 E1 CK W EP3 1 1 DQ EP2 CQ Bank Enable Truth Table EP2 Bank 0 Bank 1 Bank 2 Bank 3 VSS VSS VDD VDD EP3 VSS VDD VSS VDD E2 Active Low Active Low Active High Active High E3 Active Low Active High Active Low Active High Rev: 2.04 5/2005 10/27 (c) 2002, GSI Technology, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8170DW36/72C-333/300/250/200 Echo Clock Control in Two Banks of SigmaRAMs Read A CK Address ADV E1 E2 Bank1 E2 Bank1 W CQ Bank1 DQ_Bank1 CQ1+CQ2 CQ Bank2 DQ_Bank2 Q(B) Q(C) Q(A) Q(C) Q(D) A B C D E Read B Read C Read D Read E It should be noted that deselection of the RAM via E2 and E3 also deselects the Echo Clock output drivers. The deselection of Echo Clock drivers is always pipelined to the same degree as output data. Deselection of the RAM via E1 does not deactivate the Echo Clocks. In some applications it may be appropriate to pause between banks; to deselect both RAMs with E1 before resuming read operations. An E1 deselect at a bank switch will allow at least one clock to be issued from the new bank before the first read cycle in the bank. Although the following drawing illustrates a E1 read pause upon switching from Bank 1 to Bank 2, a write to Bank 2 would have the same effect, causing the RAM in Bank 2 to issue at least one clock before it is needed. Pipelined Read Bank Switch with E1 Deselect Read A CK Address ADV E1 E2 Bank1 E2 Bank1 W CQ_Bank1 DQ_Bank1 CQ1+CQ2 CQ_Bank2 DQ_Bank2 Q(B) Q(D) Q(A) Q(E) A B D E Read B Deselect Read D Read E Rev: 2.04 5/2005 11/27 (c) 2002, GSI Technology, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8170DW36/72C-333/300/250/200 CMOS Output Driver Impedance Control CMOS I/O SigmaRAMs are supplied with selectable (high or low) impedance output drivers. The ZQ pin allows selection between SRAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive strength (ZQ high) point-to-point applications. Double Late Write, Pipelined Read Truth Table E1 E ADV W B CK (t ) (t ) (t ) (t ) (t ) n n n n n 01 01 01 01 01 X X 1 X 0 F X T X T 0 1 0 1 0 X X X X 0 X X X X T Previous Operation X Bank Deselect X Deselect X Current Operation Bank Deselect Bank Deselect (Continue) Deselect Deselect (Continue) Write Loads new address Stores DQx if Bx = 0 Write (Abort) Loads new address No data stored Write Continue Increments address by 1 Stores DQx if Bx = 0 Write Continue (Abort) Increments address by 1 No data stored Read Loads new address Read Continue Increments address by 1 DQ/CQ (tn) ***/*** Hi-Z/Hi-Z ***/*** Hi-Z/CQ ***/*** DQ/CQ (tn+1) Hi-Z/Hi-Z Hi-Z/Hi-Z Hi-Z/CQ Hi-Z/CQ ***/*** DQ/CQ (tn+2) --------D1/CQ 01 0 T 0 0 F X ***/*** ***/*** Hi-Z/CQ 01 X X 1 X T Write ***/*** Dn-1/CQ Dn/CQ 01 X X 1 X F Write ***/*** Dn-1/CQ Hi-Z/CQ 01 01 0 X T X 0 1 1 X X X X Read ***/*** Qn-1/CQ Q1/CQ Qn/CQ ----- Notes: 1. If E2 = EP2 and E3 = EP3, then E = "T" else E = "F". 2. If one or more Bx = 0, then B = "T" else B = "F". 3. "1" = input "high"; "0" = input "low"; "X" = input "don't care"; "T" = input "true"; "F" = input "false". 4. "***" indicates that the DQ input requirement / output state and CQ output state are determined by the previous operation. 5. "---" indicates that the DQ input requirement / output state and CQ output state are determined by the next operation. 6. DQs are tristated in response to Bank Deselect, Deselect, and Write commands, one full cycle after the command is sampled. 7. CQs are tristated in response to Bank Deselect commands only, one full cycle after the command is sampled. 8. Up to three (3) Continue operations may be initiated after a Read or Write operation is initiated to burst transfer up to four (4) distinct pieces of data per single external address input. If a fourth (4th) Continue operation is initiated, the internal address wraps back to the initial external (base) address. Rev: 2.04 5/2005 12/27 (c) 2002, GSI Technology, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8170DW36/72C-333/300/250/200 Common I/O State Diagram X,F,0,X or X,X,1,X 0,T,0,1 Bank Deselect 1,T,0,X 0,T,0,0 X,F,0,X Deselect 0,T,0,1 1,T,0,X or X,X,1,X 0,T,0,0 1,T,0,X 0,T,0,0 1,T,0,X Read X,F,0,X 0,T,0,1 X,X,1,X 0,T,0,1 Write X,F,0,X X,X,1,X 0,T,0,0 0,T,0,1 1,T,0,X X,F,0,X 0,T,0,0 0,T,0,0 0,T,0,1 Read Continue X,X,1,X Write Continue X,X,1,X 1,T,0,X X,F,0,X n n+1 n+2 n+3 Key Input Command Code Clock (CK) Transition Current State (n) Next State (n + 1) Command Current State Next State Current State & Next State Definition for Read/Write Control State Diagram Notes: 1. The notation "X,X,X,X" controlling the state transitions above indicate the states of inputs E1, E, ADV, and W respectively. 2. If (E2 = EP2 and E3 = EP3) then E = "T" else E = "F". 3. "1" = input "high"; "0" = input "low"; "X" = input "don't care"; "T" = input "true"; "F" = input "false". Rev: 2.04 5/2005 13/27 (c) 2002, GSI Technology, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8170DW36/72C-333/300/250/200 Absolute Maximum Ratings (All voltages reference to VSS) Symbol VDD VDDQ VI/O VIN IIN IOUT TJ TSTG Description Voltage on VDD Pins Voltage in VDDQ Pins Voltage on I/O Pins Voltage on Other Input Pins Input Current on Any Pin Output Current on Any I/O Pin Maximum Junction Temperature Storage Temperature Value -0.5 to 2.5 -0.5 to VDD -0.5 to VDDQ + 0.5 ( 2.5 V max.) -0.5 to VDDQ + 0.5 ( 2.5 V max.) +/-100 +/-100 125 -55 to 125 Unit V V V V mA dc mA dc oC C Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect reliability of this component. Recommended Operating Conditions Power Supplies Parameter Supply Voltage 1.5 V I/O Supply Voltage 1.8 V I/O Supply Voltage Ambient Temperature (Commercial Range Versions) Ambient Temperature (Industrial Range Versions) Symbol VDD VDDQ VDDQ TA TA Min. 1.7 1.4 1.7 0 -40 Typ. 1.8 1.5 1.8 25 25 Max. 1.95 VDD VDD 70 85 Unit V V V C C Notes 1 1 Note: The part number of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. CMOS I/O DC Input Characteristics Parameter CMOS Input High Voltage CMOS Input Low Voltage Symbol VIH VIL Min. 0.65 * VDD -0.3 Typ. -- -- Max. VDD + 0.3 0.35 * VDD Unit V V Notes 1 1 Note: For devices supplied with CMOS input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers. Rev: 2.04 5/2005 14/27 (c) 2002, GSI Technology, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8170DW36/72C-333/300/250/200 Undershoot Measurement and Timing VIH VDD + 1.0 V VSS 50% VSS - 1.0 V 20% tKC VIL 50% VDD Overshoot Measurement and Timing 20% tKC Capacitance (TA = 25oC, f = 1 MHZ, VDD = 1.8 V) Parameter Input Capacitance Output Capacitance Note: This parameter is sample tested. Symbol CIN COUT Test conditions VIN = 0 V VOUT = 0 V Typ. 4 6 Max. 5 7 Unit pF pF AC Test Conditions Parameter Input high level Input low level Max. input slew rate Input reference level Output reference level Conditions VDD 0V 2 V/ns VDD/2 VDDQ/2 AC Test Load Diagram DQ RQ = 250 (HSTL I/O) 50 VT = VDDQ/2 Rev: 2.04 5/2005 15/27 (c) 2002, GSI Technology, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8170DW36/72C-333/300/250/200 Input and Output Leakage Characteristics Parameter Input Leakage Current (except mode pins) ZQ, MCH, MCL, EP2, EP3 Pin Input Current Output Leakage Current Symbol IIL IINM IOL Test Conditions VIN = 0 to VDDQ VIN = 0 to VDDQ Output Disable, VOUT = 0 to VDDQ Min. -2 uA -50 uA -2 uA Max 2 uA 50 uA 2 uA Notes -- -- -- Selectable Impedance Output Driver DC Electrical Characteristics Parameter Low Drive Output High Voltage Low Drive Output Low Voltage High Drive Output High Voltage High Drive Output Low Voltage Symbol VOHL VOLL VOHH VOLH Test Conditions IOHL = -4 mA IOLL = 4 mA IOHH = -8 mA IOLH = 8 mA Min. VDDQ - 0.4 V -- VDDQ - 0.4 V -- Max -- 0.4 V -- 0.4 V Notes 1 1 2 2 Notes: 1. ZQ = 1; High Impedance output driver setting 2. ZQ = 0; Low Impedance output driver setting Operating Currents -333 Parameter Symbol 0C to 70C 345 mA -300 0C to 70C 320 mA -250 0C to 70C 275 mA -200 0C to 70C 225 mA -40C to +85C 355 mA -40C to +85C 330 mA -40C to +85C 285 mA -40C to +85C 235 mA Test Conditions E1 VIL Max. tKHKH tKHKH Min. All other inputs VIL VIN VIH E1 VIH Min. or tKHKH tKHKH Min. All other inputs VIL VIN VIH E2 or E3 False tKHKH tKHKH Min. All other inputs VIL VIN VIH Device Deselected All inputs VSS + 0.10 V VIN VDD - 0.10 V Operating Current x72 IDDP (PL) Chip Disable Current x72 ISB1 (PL) 75 mA 85 mA 70 mA 80 mA 65 mA 75 mA 60 mA 70 mA Bank Deselect Current x72 ISB2 (PL) 75 mA 85 mA 70 mA 80 mA 65 mA 75 mA 60 mA 70 mA CMOS Deselect Current IDD3 45 mA 55 mA 45 mA 55 mA 45 mA 55 mA 45 mA 55 mA Rev: 2.04 5/2005 16/27 (c) 2002, GSI Technology, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8170DW36/72C-333/300/250/200 AC Electrical Characteristics Parameter Clock Cycle Time Clock High Time Clock Low Time Clock High to Echo Clock Low-Z Clock High to Echo Clock High Clock Low to Echo Clock Low Clock High to Echo Clock High-Z Clock High to Output Low-Z Clock High to Output Valid Clock High to Output Invalid Clock High to Output High-Z Echo Clock High to Output Valid Echo Clock High to Output Invalid Address Valid to Clock High Clock High to Address Don't Care Enable Valid to Clock High Clock High to Enable Don't Care Write Valid to Clock High Clock High to Write Don't Care Byte Write Valid to Clock High Clock High to Byte Write Don't Care Data In Valid to Clock High Clock High to Data In Don't Care ADV Valid to Clock High Clock High to ADV Don't Care Symbol tKHKH tKHKL tKLKH tKHCX1 tKHCH tKLCL tKHCZ tKHQX1 tKHQV tKHQX tKHQZ tCHQV tCHQX tAVKH tKHAX tEVKH tKHEX tWVKH tKHWX tBVKH tKHBX tDVKH tKHDX tadvVKH tKHadvX -333 Min 3.0 1.2 1.2 0.5 -- -- -- 0.5 -- 0.5 -- -- -0.35 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.5 0.4 0.6 0.4 Max -- -- -- -- 1.8 1.8 1.8 -- 1.8 -- 1.8 0.35 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.5 0.5 -300 Min 3.3 1.3 1.3 0.5 Max -- -- -- -- 1.8 1.8 1.8 -- 1.8 -- 1.8 0.38 -- -- -- -- -- -- -- -- -- -- -- -- -- -250 Min 4.0 1.6 1.6 0.5 -- -- -- 0.5 -- 0.5 -- -- -0.45 0.8 0.5 0.8 0.5 0.8 0.5 0.8 0.5 0.5 0.5 0.8 0.5 Max -- -- -- -- 2.1 2.1 2.1 -- 2.1 -- 2.1 0.45 -- -- -- -- -- -- -- -- -- -- -- -- -- -200 Min 5.0 1.8 1.8 0.5 -- -- -- 0.5 -- 0.5 -- -- -0.5 0.8 0.5 0.8 0.5 0.8 0.5 0.8 0.5 0.8 0.5 0.8 0.5 Max -- -- -- -- 2.1 2.1 2.1 -- 2.25 -- 2.1 0.5 -- -- -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes -- -- -- 2 -- 1, 2 1 -- -- 1 2 2 -- -- -- -- -- -- -- -- -- -- -- -- -0.38 0.7 0.4 0.7 0.4 0.7 0.4 0.7 0.4 0.5 0.4 0.7 0.4 Notes: 1. Measured at 100 mV from steady state. Not 100% tested. 2. Guaranteed by design. Not 100% tested. 3. For any specific temperature and voltage tKHCZ < tKHCX1. Rev: 2.04 5/2005 17/27 (c) 2002, GSI Technology, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8170DW36/72C-333/300/250/200 Timing Parameter Key--Pipelined Read Cycle Timing KHKL CK KLKH KHKH KHAX B AVKH A E2 A KHQV KHQX1 DQ(Data Out) Q(A) Q(B) KHQZ KHQX KLCL KHCH CQ CHQV CHQX KHCX1 KHCZ Timing Parameter Key--Double Late Write Mode Control and Data In Timing CK tKHAX tAVKH A A B C tnVKH tKHnX E1, E2, E3, W, Bx, ADV tDVKH DQ (Data In) DA tKHDX Note: tnVKH = tEVKH, tWVKH, tBVKH, etc. and tKHnX = tKHEX, tKHWX, tKHBX, etc. Rev: 2.04 5/2005 18/27 (c) 2002, GSI Technology, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8170DW36/72C-333/300/250/200 JTAG Port Operation Overview The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output drivers are powered by VDDQ. Disabling the JTAG Port It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected. JTAG Pin Descriptions Pin TCK Pin Name Test Clock I/O In Description Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level. The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level. TMS Test Mode Select In TDI Test Data In In TDO Test Data Out Output that is active depending on the state of the TAP state machine. Output changes in Out response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up. JTAG Port Registers Overview The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins. Instruction Register The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state. Bypass Register The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM's JTAG Port to another device in the scan chain with as little delay as possible. Boundary Scan Register The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM's input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port's TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Rev: 2.04 5/2005 19/27 (c) 2002, GSI Technology, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8170DW36/72C-333/300/250/200 Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. JTAG TAP Block Diagram * * * 108 * * * * * * * * 1 Boundary Scan Register 0 Bypass Register 210 0 Instruction Register TDI ID Code Register 31 30 29 TDO * *** 210 Control Signals TMS TCK Test Access Port (TAP) Controller Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. ID Register Contents Die Revision Code GSI Technology JEDEC Vendor ID Code Presence Register 0 1 Not Used I/O Configuration Bit # x36 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 011011001 Rev: 2.04 5/2005 20/27 (c) 2002, GSI Technology, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8170DW36/72C-333/300/250/200 Tap Controller Instruction Set Overview There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers. When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table. JTAG Tap Controller State Diagram 1 Test Logic Reset 0 1 1 1 0 Run Test Idle Select DR 0 1 Select IR 0 1 Capture DR 0 Capture IR 0 Shift DR 1 1 0 1 Shift IR 1 0 Exit1 DR 0 Exit1 IR 0 Pause DR 1 0 Pause IR 1 0 Exit2 DR 1 0 Exit2 IR 1 0 Update DR 1 0 Update IR 1 0 Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. Rev: 2.04 5/2005 21/27 (c) 2002, GSI Technology, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8170DW36/72C-333/300/250/200 SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM's input pins; therefore, the RAM's internal state is still determined by its input pins. Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register's contents, in parallel, on the RAM's data output drivers on the falling edge of TCK when the controller is in the Update-IR state. Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM's input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM's output pins drive out the value of the Boundary Scan Register location with which each output pin is associated. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (highZ) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction. Rev: 2.04 5/2005 22/27 (c) 2002, GSI Technology, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8170DW36/72C-333/300/250/200 JTAG Port AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Conditions VDD - 0.2 V 0.2 V 1 V/ns VDDQ/2 VDDQ/2 DQ JTAG Port AC Test Load 50 VDDQ/2 * Distributed Test Jig Capacitance 30pF* Notes: 1. Include scope and jig capacitance. 2. Test conditions as as shown unless otherwise noted. JTAG TAP Instruction Set Summary Instruction EXTEST IDCODE SAMPLE-Z RFU SAMPLE/PRELOAD GSI RFU BYPASS Code 000 001 010 011 100 101 110 111 Description Places the Boundary Scan Register between TDI and TDO. Preloads ID Register and places it between TDI and TDO. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all RAM output drivers to High-Z. Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. GSI private instruction. Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. Places Bypass Register between TDI and TDO. Notes 1 1, 2 1 1 1 1 1 1 Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. Rev: 2.04 5/2005 23/27 (c) 2002, GSI Technology, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8170DW36/72C-333/300/250/200 JTAG Port Recommended Operating Conditions and DC Characteristics Parameter 1.8 V Test Port Input High Voltage 1.8 V Test Port Input Low Voltage TMS, TCK and TDI Input Leakage Current TMS, TCK and TDI Input Leakage Current TDO Output Leakage Current Test Port Output High Voltage Test Port Output Low Voltage Test Port Output CMOS High Test Port Output CMOS Low Symbol VIHJ2 VILJ2 IINHJ IINLJ IOLJ VOHJ VOLJ VOHJC VOLJC Min. 0.6 * VDD -0.3 -300 -1 -1 1.7 -- VDDQ - 100 mV -- Max. VDD +0.3 0.3 * VDD 1 100 1 -- 0.4 -- 100 mV Unit Notes V V uA uA uA V V V V 1 1 2 3 4 5, 6 5, 7 5, 8 5, 9 Notes: 1. Input Under/overshoot voltage must be -2 V > Vi < VDDn +2 V not to exceed 2.5 V maximum, with a pulse width not to exceed 20% tTKC. 2. VILJ VIN VDDn 3. 0 V VIN VILJn 4. Output Disable, VOUT = 0 to VDDn 5. The TDO output driver is served by the VDDQ supply. 6. IOHJ = -4 mA 7. IOLJ = + 4 mA 8. IOHJC = -100 uA 9. IOHJC = +100 uA JTAG Port Timing Diagram tTKC TCK tTH tTS TDI tTH tTS TMS tTKQ TDO tTH tTS Parallel SRAM input tTKH tTKL Rev: 2.04 5/2005 24/27 (c) 2002, GSI Technology, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8170DW36/72C-333/300/250/200 Parameter TCK Cycle Time TCK Low to TDO Valid TCK High Pulse Width TCK Low Pulse Width TDI & TMS Set Up Time TDI & TMS Hold Time Symbol tTKC tTKQ tTKH tTKL tTS tTH Min 50 -- 20 20 10 10 Max -- 20 -- -- -- -- Unit ns ns ns ns ns ns 209 BGA Package Drawing (Package C) 14 mm x 22 mm Body, 1.0 mm Bump Pitch, 11 x 19 Bump Array C A1 A aaa D D1 Side View e Bottom View E1 b e Symbol A A1 b c D Rev 1.0 Min -- 0.40 0.50 0.31 21.9 Typ -- 0.50 0.60 0.36 22.0 Max 1.70 0.60 0.70 0.38 22.1 Units mm mm mm mm mm Symbol D1 E E1 e aaa Min -- 13.9 -- -- -- Typ 18.0 (BSC) 14.0 10.0 (BSC) 1.00 (BSC) 0.15 E Max -- 14.1 -- -- -- Units mm mm mm mm mm Rev: 2.04 5/2005 25/27 (c) 2002, GSI Technology, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8170DW36/72C-333/300/250/200 Ordering Information--GSI SigmaRAM Org 256K x 72 256K x 72 256K x 72 256K x 72 256K x 72 256K x 72 256K x 72 256K x 72 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 Part Number GS8170DW72C-333 GS8170DW72C-300 GS8170DW72C-250 GS8170DW72C-200 GS8170DW72C-333I GS8170DW72C-300I GS8170DW72C-250I GS8170DW72C-200I GS8170DW36C-333 GS8170DW36C-300 GS8170DW36C-250 GS8170DW36C-200 GS8170DW36C-333I GS8170DW36C-300I GS8170DW36C-250I GS8170DW36C-200I Type Double Late Write S1x1Dp SRAM Double Late Write S1x1Dp SRAM Double Late Write S1x1Dp SRAM Double Late Write S1x1Dp SRAM Double Late Write S1x1Dp SRAM Double Late Write S1x1Dp SRAM Double Late Write S1x1Dp SRAM Double Late Write S1x1Dp SRAM Double Late Write 1x1Dp SRAM Double Late Write 1x1Dp SRAM Double Late Write 1x1Dp SRAM Double Late Write 1x1Dp SRAM Double Late Write 1x1Dp SRAM Double Late Write 1x1Dp SRAM Double Late Write 1x1Dp SRAM Double Late Write 1x1Dp SRAM I/O CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS Speed (MHz) 333 MHz 300 MHz 250 MHz 200 MHz 333 MHz 300 MHz 250 MHz 200 MHz 333 MHz 300 MHz 250 MHz 200 MHz 333 MHz 300 MHz 250 MHz 200 MHz TA C C C C I I I I C C C C I I I I Notes: 1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS817xx36C-300T. 2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. Rev: 2.04 5/2005 26/27 (c) 2002, GSI Technology, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8170DW36/72C-333/300/250/200 18Mb Sync RAM Datasheet Revision History DS/DateRev. Code: Old; New 8170W18_r1 8170W18_r1; 8170W18_r1_01 8170W18_r1_01; 8170W18_r2 8170W18_r2; 8170W18_r2_01 8170W18_r2_01; 8170W18_r2_02 8170Wxx_r2_02; 8170Wxx_r2_03 8170Wxx_r2_03; 8170Wxx_r2_04 Content Content Content/format Content/format Content/format Content Types of Changes Format or Content Page;Revisions;Reason * Creation of new datasheet * Removed all references to FT mode * Complete rewrite (DC from 36Mb) * Added 200 MHz speed bin * Updated format * Pervasive edit * Added x72 information to ordering information * Updated format * Removed Preliminary banner due to qualification * Added 1.5 V I/O information Rev: 2.04 5/2005 27/27 (c) 2002, GSI Technology, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. |
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